Driven by the growth of mixed work and network geographic distribution, the demand for bandwidth and security in network infrastructure is redefining boundaryless networks. According to 650 Group's prediction, driven by the application of artificial intelligence/machine learning (AI/ML), the total port bandwidth of 400G (gigabits per second) and 800G will grow at a rate of over 50% per year. This rapid growth is expanding the transition to 112G PAM4 connectivity, not only for cloud data centers and telecom service providers' switches and routers, but also for enterprise Ethernet switching platforms. Microchip Technology Inc. is responding to market demand with its META-DX2 Ethernet PHY (Physical Layer) product portfolio and launching a new META-DX2+PHY series. This series of products is the industry's first solution that integrates 1.6T (terabit/second) wire speed end-to-end encryption and port aggregation capabilities, helping enterprise Ethernet switches, security devices, cloud interconnect routers, and optical transmission systems transition to 112G PAM4 connections while maintaining the most compact size.
Babak Samimi, Enterprise Vice President of Microchip's Communications Business Unit, stated, "We are launching four new META-DX2+Ethernet PHY models aimed at driving the industry's transition to 112G PAM4 connectivity supported by a combination of META-DX retimers and PHY. Combined with the META-DX2L re timer, Microchip can now provide a complete chipset that meets all connectivity requirements from re timing, gearbox applications to advanced PHY functionality. By providing hardware and software pin compatibility, customers can leverage architecture design in their enterprise, data center, and service provider switching and routing systems, offering advanced features enabled on demand through software subscription models, including end-to-end security, multi rate port aggregation, and precise timestamps
Microchip launches the industry's first Terabit premium secure Ethernet PHY series product with port aggregation capabilities, helping enterprises and the cloud interconnect (Figure 1)
META-DX2+has a configurable 1.6T data path architecture, which is twice superior to its nearest competitors in terms of total transmission capacity and uninterrupted 2:1 protection switch reuse mode achieved by its unique ShiftIO capability. The flexible XpandIO port aggregation capability optimizes the port utilization of routers/switches and supports low-speed traffic. In addition, these devices also support IEEE 1588 Class C/D Precision Time Protocol (PTP) to achieve precise nanosecond timestamps required for 5G and enterprise critical business services. Microchip provides a range of pin compatible retimers and advanced PHY product combinations with encryption options, allowing developers to extend their designs by adding MACsec and IPsec on top of general-purpose board designs and software development kits (SDKs).
The differentiated features of META-DX2+include:
● Dual 800 GbE, quad 400 GbE, and 16x 100/50/25/10/1 GbE MAC/PHY
The integrated 1.6T MACsec/IPsec engine can offload encryption from the packet processor, making it easier for the system to scale to higher bandwidths and providing end-to-end security
Compared to the competitive solution that requires two devices to provide the same 1.6T gearbox and uninterrupted 2:1 multiplexing mode, it can save more than 20% of circuit board costs
XpandIO enables low-speed Ethernet clients to aggregate ports on higher speed Ethernet interfaces, optimizing for enterprise platforms
The combination of ShiftIO functionality and highly configurable integrated intersections enables flexible connections between external switches, processors, and optical devices
The variable model of 112G PAM4 SerDes with 48 or 32 Long Range (LR) functionality, with programmability to optimize power and performance.
● Supports Ethernet OTN、 Fiber Channel and proprietary data rates for AI/ML applications
Alan Weckel, founder and technical analyst of 650 Group, said, "As the industry transitions to a 112G PAM4 serial ecosystem for high-density routers and switches, line speed encryption and efficient utilization of port capacity are becoming increasingly important. Microchip's META-DX2+series will play an important role in implementing MACsec and IPsec encryption, optimizing port capacity through port aggregation, and flexibly connecting routing/switching chips to multi rate 400G and 800G optical devices
Like the META-DX2L re timer, the new series META-DX2+PHY can be paired with Microchip's PolarFire ® FPGA, ZL30632 high-performance PLL, oscillator, regulator, and other components are used together. These components have been pre validated as a system, which helps accelerate design and production.
development tool
The Microchip second-generation Ethernet PHY SDK for the META-DX2 series has reduced development costs through on-site validation of API libraries and firmware. This SDK supports all META-DX2L and META-DX2+PHY devices in this series. This includes support for the Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extension to enable cross platform support for META-DX2 PHY in various Network Operating Systems (NOS) that support SAI.
